The present invention claims priority to its priority document No. 2001-334360 filed in the Japanese Patent Office on Oct. 31, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a digital to analog converter comprising a ferroelectric non-volatile semiconductor memory (so-called FERAMS), and to a method of converting digital data to analog data using the digital to analog converter above.
2. Description of the Related Art
There are various known digital to analog converters (hereinafter abbreviated as D/A converters) such as those using a load resistor, or a ladder resistor network, and those which obtain analog output by converting digital input into a pulse number or pulse width and passing it through a low-pass filter.
In general, these conventional D/A converters do not have memory functions. Therefore, it is difficult for a conventional D/A converter by itself to temporally control the outputting of the converted analog data, and in order to retain or edit the converted analog data, a separate device or storage medium is required. In addition, in converting a large volume of digital data, a high-speed D/A converter is required, and converting a large volume of digital data to analog data is thus difficult.
Therefore, one aspect of the present invention is to provide a novel digital to analog converter which, in the conversion of digital data to analog data, enables temporal controlling of the outputting of the converted analog data, and/or which enables high-speed conversion of a large volume of digital data to analog data, and is also to provide a method for converting digital data to analog data using such a digital to analog converter.
A digital to analog converter according to a first aspect of the present invention is a digital to analog converter including a ferroelectric non-volatile semiconductor memory, wherein
the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line; and
(B) N (where Nxe2x89xa72) memory units;
each of the memory unit comprises:
(B-1) a selection transistor;
(B-2) a memory cell comprising a first electrode, a ferroelectric layer and a second electrode; and
(B-3) a plate line;
wherein the first electrode is connected to the data line via the selection transistor,
the second electrode is connected to the plate line, and
the area of the ferroelectric layer of the individual memory cells differs among the memory cells.
A digital to analog converter according to a second aspect of the present invention is a digital to analog converter comprising a ferroelectric non-volatile semiconductor memory,
wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) a memory unit comprising M (where Mxe2x89xa72) memory cells; and
(C) M plate lines,
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrode of the memory cells is shared in the memory unit and is connected to the data line,
the second electrode of the mth (where m=1, 2, . . . M) memory cell in the memory unit is connected to the mth plate line, and
the area of the ferroelectric layer of the individual memory cells differs among the memory cells.
A digital to analog converter according to a third aspect of the present invention is a digital to analog converter including a ferroelectric non-volatile semiconductor memory,
wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) N (where Nxe2x89xa72) memory units individually comprising M (where Mxe2x89xa72) memory cells; and
(C) Mxc3x97N plate lines;
wherein the N memory units are layered with an insulation layer in between each,
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each memory unit, the first electrode of the memory cell is shared, and is connected to the data line,
the second electrode of the mth (where m=1, 2, . . . M) memory cell in the memory unit of the nth (where n=1, 2, . . . N) layer is connected to the [(nxe2x88x921)M+m]th plate line, and
the area of the ferroelectric layer of the memory cells differs among the memory cells.
A digital to analog converter according to a fourth aspect of the present invention is a digital to analog converter including a ferroelectric non-volatile semiconductor memory,
wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) N (where Nxe2x89xa72) selection transistors;
(C) N memory units each comprising M (where Mxe2x89xa72) memory cells; and
(D) M plate lines;
wherein each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each of the memory units, the first electrode of the memory cells is shared,
the shared first electrode of the nth (where n=1, 2, . . . N) memory unit is connected to the data line via the nth selection transistor,
in the nth memory unit, the second electrode of the mth (where m=1, 2, . . . M) memory cell is connected to the mth plate line which is shared between the memory units, and
the area of the ferroelectric layer of the memory cells in each of the memory units differs among the memory cells.
A digital to analog converter according to a fifth aspect of the present invention is a digital to analog converter comprising a ferroelectric non-volatile semiconductor memory,
wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) N (where Nxe2x89xa72) data lines;
(B) N selection transistors;
(C) N memory units each comprising M (where Mxe2x89xa72) memory cells; and
(D) M plate lines;
N memory units are layered with an insulation layer in between each,
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each of the memory units, the first electrode of the memory cells is shared,
the shared first electrode in the memory unit of the nth (where n=1, 2, . . . N) layer is connected to the nth data line via the nth selection transistor,
the second electrode of the mth (where m=1, 2, . . . M) memory cell in the memory unit of the nth layer is connected to the mth plate line which is shared between the memory units, and
the area of the ferroelectric layer of the memory cells in each of the memory units differs among the memory cells.
A method for converting digital data to analog data according to the first aspect of the present invention is a method for converting a digital data of M bits to analog data using a digital to analog converter including a ferroelectric non-volatile semiconductor memory, wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line; and
(B) N (where Nxe2x89xa72) memory units;
each of the memory units comprises:
(B-1) a selection transistor;
(B-2) a memory cell comprising a first electrode, a ferroelectric layer and a second electrode; and
(B-3) a plate line;
the first electrode is connected to the data line via the selection transistor,
the second electrode is connected to the plate line, and
the area of the ferroelectric layer of the individual memory cells differs among the memory cells, and
the method comprises the steps of:
setting the selection transistor to a conductive condition and driving the data line and the plate line to write the mth binary data (where m=1, 2, . . . M) in the memory cells of the mth memory unit;
setting the selection transistor to a conductive condition, and driving all plate lines to simultaneously read out data from the memory cells in all of the memory units; and
outputting the resultant electric potential which is generated across the data line.
A method for converting digital data to analog data according to the second aspect of the present invention is a method for converting M bits of digital data to analog data using a digital to analog converter,
wherein the digital to analog converter includes a ferroelectric non-volatile semiconductor memory,
the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) a memory unit comprising M (where Mxe2x89xa72) memory cells; and
(C) M plate lines,
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in the memory unit, the first electrode of the memory cells is shared, and is connected to the data line,
the second electrode of the mth (where m=1, 2, . . . M) memory cell in the memory unit is connected to the mth plate line,
the area of the ferroelectric layer of the individual memory cells differs among the memory cells, and
the method comprises the steps of:
driving the data line and the plate line to write the mth binary data in the mth memory cell;
activating all plate lines to simultaneously read out data from all memory cells; and
outputting the resultant electric potential which is generated across the data line.
A method for converting digital data to analog data according to the third aspect of the present invention is a method for converting Mxc3x97N bits of digital data to analog data using a digital to analog converter,
wherein the digital to analog converter includes a ferroelectric non-volatile semiconductor memory,
the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) N (where Nxe2x89xa72) memory units each comprising M (where Mxe2x89xa72) memory cells; and
(C) Mxc3x97N plate lines;
the N memory units are layered with an insulating layer in between each,
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each memory unit, the first electrode is shared, and is connected to the data line,
in the memory unit of the nth layer (where n=1, 2, . . . N), the second electrode of the mth (where m=1, 2, . . . M) memory cell is connected to the [(nxe2x88x921)M+m]th plate line,
the area of the ferroelectric material layer of the individual memory cells differs among the memory cells, and
the method comprises the steps of:
driving the data line and the plate line to write the binary data of the [(nxe2x88x921)M+m]th bit in the [(nxe2x88x921)M+m]th memory cell; and
activating all plate lines to thereby simultaneously read out data from all memory cells and output the resultant electric potential which is generated across the data line.
A method for converting digital data to analog data according to the fourth aspect of the present invention is a method for converting M bits of digital data to analog data using a digital to analog converter,
wherein the digital to analog converter includes a ferroelectric non-volatile semiconductor memory,
the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) N (where Nxe2x89xa72) selection transistors;
(C) N memory units each comprising M (where Mxe2x89xa72) memory cells; and
(D) M plate lines;
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each of the memory units, the first electrode of the memory cells is shared,
the shared first electrode in the nth (where n=1, 2, . . . N) memory unit is connected to the data line via the nth selection transistor,
the second electrode of the mth (where m=1, 2, . . . M) memory cell in the nth memory unit is connected to the mth plate line which is shared between the memory units,
in each of the memory units, the area of the ferroelectric layer of the memory cells differs among the memory cells, and
the method comprises the steps of:
setting the selection transistor to a conductive condition, and driving all the data lines and the plate lines to write a binary data of the mth bit in the mth memory cell in the nth memory unit;
setting the nth selection transistor to a conductive condition, and driving all the plate lines to simultaneously read out data from all the memory cells in the nth memory unit; and
outputting the resultant electric potential which is generated across the data line.
A method for converting digital data to analog data according to the fifth aspect of the present invention is a method for converting Mxc3x97N bits of digital data to analog data using a digital to analog converter, wherein
the digital to analog converter includes a ferroelectric non-volatile semiconductor memory,
the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) N (where Nxe2x89xa72) selection transistors;
(C) N memory units each comprising M (where Mxe2x89xa72) memory cells; and
(D) M plate lines;
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each of the memory units, the first electrode of the memory cells is shared,
the shared first electrode in the nth (where n=1, 2, . . . N) memory unit is connected to the data line via the nth selection transistor,
in the nth memory unit, the second electrode of the mth (where m=1, 2, . . . M) memory cell is connected to the mth plate line which is shared between the memory units,
the area of the ferroelectric layer of the memory cells differs among the memory cells, and
the method comprises the steps of:
setting the nth selection transistor to a conductive condition, and driving the data line and the plate line to write a binary data of the [(nxe2x88x921)M+m]th bit in the mth memory cell in the nth memory unit;
setting all the selection transistors to a conductive condition, and driving all the plate lines to simultaneously read out data from all the memory cells in the nth memory unit; and
outputting the resultant electric potential which is generated across the data line.
A method for converting digital data to analog data according to a sixth aspect of the present invention is a method for converting M bits of digital data to analog data using a digital to analog converter, wherein
the digital to analog converter includes a ferroelectric non-volatile semiconductor memory,
the ferroelectric non-volatile semiconductor memory comprises:
(A) N (where Nxe2x89xa72) data lines;
(B) N selection transistors;
(C) N memory units each comprising M (where Mxe2x89xa72) memory cells; and
(D) M plate lines;
the N memory units are layered with an insulation layer in between each,
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each of the memory units, the first electrode of the memory cells is shared,
the shared first electrode in the memory unit of the nth (where n=1, 2, . . . N) layer is connected to the nth data line via the nth selection transistor,
in the memory unit of the nth layer, the second electrode of the mth (where m=1, 2, . . . M) memory cell is connected to the mth plate line which is shared between the memory units,
the area of the ferroelectric layer of the memory cells in each of the memory units differs among the memory cells, and
the method comprises the steps of:
setting the nth selection transistor to a conductive condition, and driving the nth data line and the mth plate line to write a binary data of the mth bit in the mth memory cell in the memory unit of the nth layer;
setting the nth selection transistor to a conductive condition, and driving all the plate lines to simultaneously read out data from all the memory cells in the memory unit of the nth layer; and
outputting the resultant electric potential which is generated across the nth data line.
In the digital to analog converter according to any of the first to fifth aspects of the present invention (hereinafter referred to as a D/A converter) and the method for converting digital data to analog data according to any of the first to sixth aspects of the present invention (hereinafter referred to as a D/A conversion method), the rise in electric potential xcex94V is theoretically given by equation (1) below, if the amount of polarization per unit area of the ferroelectric layer, the area of the mth (m=1, 2, . . . M) memory cell MCm, and the total capacitance of the memory cells and data lines are, respectively, assumed to be P, Am and Co. Note that Dm represents the binary data stored in the memory cell MCm, and has either the value of xe2x80x9c0xe2x80x9d or xe2x80x9c1.xe2x80x9d                              Δ          ⁢                      xe2x80x83                    ⁢          V                =                              (                          P              /                              C                0                                      )                    ⁢                                    ∑                              m                =                1                            M                        ⁢                          (                                                A                  m                                ·                                  D                  m                                            )                                                          [Equation  (1)]            
While the area of the ferroelectric layer of each of the memory cells may essentially be arbitrary so long as the digital data input and the analog data output correspond one to one with each other, xcex94V will have a linear value if Am=2(mxe2x88x921)A1 is satisfied. The electric potential generated across the data line is generally outputted after being amplified using a sense amplifier, and the area may be adjusted as deemed appropriate depending on the characteristics of the sense amplifier or on the desired output characteristics. In certain cases, the configuration may be such that a compensatory circuit is provided for output compensation so as to obtain linearity. An amplifier for amplifying the analog data may further be provided in the stages following the sense amplifier.
In the present invention, by varying the size of the ferroelectric layer of each of the memory cells, the area of the ferroelectric layer of the memory cells may be varied. By keeping the widths of the first electrodes uniform and varying the, widths of the plate lines, by keeping the widths of the plate lines uniform and varying the widths of the first electrodes, or by varying the widths of the first electrodes and the plate lines, the size of the ferroelectric layer of each of the memory cells may be varied. In addition, by providing one or more unit memory cells in each of the memory cells, and varying the number of unit memory cells in the memory cells, the area of the ferroelectric layer of the memory cells may be varied.
In the present invention, one need only satisfy the condition Mxe2x89xa72, but the value of M or Mxc3x97N must coincide with the number of bits of the digital data to be converted, an example of which includes involutions of 2 (2, 4, 8 . . . ). In addition, in the D/A converter according to the third to fifth aspects of the present invention or in the D/A conversion method according to the third to sixth aspects of the present invention, one need only satisfy the condition Nxe2x89xa72 where an example of the practical values for N include involutions of 2 (2, 4, 8 . . . ). In the D/A conversion method according to the fifth embodiment of the present invention, the value of Mxc3x97N must coincide with the number of bits of the digital data to be converted.
In the D/A converter according to the third aspect of the present invention, or the D/A conversion method according to the third aspect of the present invention, the memory units of the ferroelectric non-volatile semiconductor memory in a plurality of D/A converters may be layered with an insulation layer between successive layers. In the D/A converter according to the fourth aspect of the present invention, or the D/A conversion method according to the fourth or fifth aspect of the present invention, the N memory units may be formed on the same insulation layer, or they may be layered with an insulation layer between successive layers.
In the D/A converter according to the second or third aspect of the present invention, or the D/A conversion method according to the second or third aspect of the present invention, in a case where one data line is shared between a plurality of D/A converters, in other words, where a plurality of D/A converters are connected to a single data line, the ferroelectric non-volatile semiconductor memory must have a configuration in which a selection transistor is additionally provided and the first electrode shared in the memory unit is connected to the data line via the selection transistor.
In the D/A converter according to the third or fifth aspect of the present invention, the D/A conversion method according to the third or sixth aspect of the present invention, the D/A converter according to a preferred embodiment of the fourth aspect of the present invention, or the D/A conversion method according to preferred embodiments of the forth or fifth aspect of the present invention, by structuring the memory unit in three-dimensional layers, a restriction effected by the number of transistors which occupying the surface of the semiconductor substrate is removed, the storage capacity may be increased dramatically, and the effective occupied area per bit of storage may be reduced considerably.
In the D/A converter according to the third or fifth aspect of the present invention, the D/A conversion method according to the third or sixth aspect of the present invention, the D/A converter according to a preferred embodiment of the fourth aspect of the present invention, or the D/A conversion method according to a preferred embodiment of the forth or fifth aspect of the present invention, it is preferable that the crystallization temperature of the ferroelectric layer of the memory cells in the memory unit located in the upper area be lower than the crystallization temperature of the ferroelectric layer of the memory cell in the memory unit located in the lower area. The crystallization temperature of the ferroelectric layer of the memory cells may be found using, for example, an X-ray diffractometer or surface scanning electron microscope. More specifically, the crystallization temperature of the ferroelectric layer can be found by first forming the ferroelectric material layer, performing on the ferroelectric layer a thermal treatment for facilitating crystallization under varied temperatures, performing an X-ray diffraction analysis on the ferroelectric layer after the thermal treatment, and evaluating the diffraction pattern intensity (height of diffraction peaks) specific to the ferroelectric material.
In manufacturing a ferroelectric non-volatile semiconductor memory with a construction in which the memory units are layered, a thermal treatment (referred to as a crystallization thermal treatment) must be performed a number of times equaling the number of layered memory units in order to crystallize the ferroelectric layer or a ferroelectric thin film of the ferroelectric layer. As a result, the memory units located in the lower stages undergo a longer period of crystallization thermal treatment, and the memory units located in the upper stages undergo a shorter period of crystallization thermal treatment. Therefore, if a crystallization thermal treatment optimal for the memory units located in the upper stages is performed, there are risks that the memory units located in the lower stages suffer an excessive thermal load, and that degradation in the characteristics of the memory units located in the lower stages may occur. There is an alternative method in which the crystallization thermal treatment is performed once after the multi-layered memory units are formed, but in this case, there is a high likelihood that a large volume change of the ferroelectric layers occurs during crystallization, or that degassing occurs in each of the ferroelectric layers, and problems such as cracks in or peeling of the ferroelectric layers are likely to occur. Such degradation in the characteristics of the memory cells of the memory units located in the lower stages will not occur if the crystallization temperature of the ferroelectric layer of the memory units located in the upper stages is lower than the crystallization temperature of the ferroelectric layer of the memory units located in the lower stages even if the crystallization thermal treatment is carried out a number of times equaling the number of the layered memory units. Further, a crystallization treatment may be performed on the memory cells in the memory unit of each layer under optimal conditions, thereby producing a ferroelectric non-volatile semiconductor memory with superior characteristics. Table 1 below shows the crystallization temperatures of typical materials for the ferroelectric layer, but materials for the ferroelectric layer are by no means limited thereto.
Materials for the ferroelectric layer in the present invention include bismuth (Bi) layered compounds, or more specifically, ferroelectric materials of a Bi-based layered perovskite type. The ferroelectric materials of a Bi-based layered perovskite type belong to the so-called group of non-stoichiometric compounds, and have a tolerance for compositional shifts on both sites, the metal element and the anion (oxygen, etc). It is also not unusual that optimal electric characteristics appear at a composition slightly off the stoichiometric composition. The Bi-based layered perovskite type ferroelectric material can typically be expressed by a general formula (Bi2O2)2+(Amxe2x88x921BmO3m+1)2xe2x88x92, where xe2x80x9cAxe2x80x9d represents any one metal selected from the group comprising Bi, Pb, Ba, Sr, Ca, Na, K, Cd and so forth, xe2x80x9cBxe2x80x9d represents any one metal or a combination of a plurality of metals at an arbitrary ratio selected from the group comprising Ti, Nb, Ta, W, Mo, Fe, Co and Cr, and m represents an integer of 1 or larger.
The material for the ferroelectric layer preferably contains, as its dominant crystalline phase, a crystalline phase expressed by
(BiX, Sr1xe2x88x92X)2(SrY, Bi1xe2x88x92Y)(TaZ, Nb1xe2x88x92Z)2Odxe2x80x83xe2x80x83Formula (1) 
(where 0.9xe2x89xa6Xxe2x89xa61.0, 0.7xe2x89xa6Yxe2x89xa61.0, 0xe2x89xa6Zxe2x89xa61.0 and 8.7xe2x89xa6dxe2x89xa69.3). It is also preferable that the material for the ferroelectric layer contains, as its dominant crystalline phase, a crystal phase expressed by
BiXSrYTa2Odxe2x80x83xe2x80x83Formula (2) 
(where X+Y=3, 0.7xe2x89xa6Yxe2x89xa61.3 and 8.7xe2x89xa6dxe2x89xa69.3). In these cases, it is further preferable that the crystalline phase expressed by formula (1) or (2) is contained as the dominant crystalline phase in a percentage of 85% or more. It should be noted that the expression (BiX, Sr1xe2x88x92X) in formula (1) means that the site ordinarily occupied by Bi in the crystal structure is occupied by Sr, and that the ratio of Bi and Sr is given by X:(1xe2x88x92X). Similarly, the expression (SrY, Bi1xe2x88x92Y) means that the site ordinarily occupied by Sr in the crystal structure is occupied by Bi, and that the ratio of Sr and Bi is given by Y:(1xe2x88x92Y). The materials for the ferroelectric layer containing, as the dominant crystalline phase, the crystalline phase expressed by formula (1) or (2) may sometimes contain a slight amount of oxides of Bi, oxides of Ta and Nb, or composite oxides of Bi, Ta and Nb.
The materials for the ferroelectric layer may also contain a crystalline phase expressed by
BiX(Sr, Ca, Ba)Y(TaZ, Nb1xe2x88x92Z)2Odxe2x80x83xe2x80x83formula (3) 
(where 1.7xe2x89xa6Xxe2x89xa62.5, 0.6xe2x89xa6Yxe2x89xa61.2, 0xe2x89xa6Zxe2x89xa61.0 and 8.0xe2x89xa6dxe2x89xa610.0). It should be noted that the expression (Sr, Ca, Ba) expresses a single element selected from the group consisting of Sr, Ca and Ba. Stoichiometric expressions of the composition of the materials for the ferroelectric layer expressed by these formulae include, for example, Bi2SrTa2O9, Bi2SrNb2O9, Bi2BaTa2O9, Bi2Sr(Ta,Nb)2O9 and so forth. As the material for the ferroelectric layer, Bi4SrTi4O15, Bi3TiNbO9, Bi3TiTaO9, Bi4Ti3O12, Bi2PbTa2O9 and so forth may also be cited as examples, and the ratio of the individual metal elements may be varied as long as the crystal structure remains unchanged. In other words, there may be compositional shifts at both sites, the metal elements and the oxygen element.
Still other examples of the material for the ferroelectric layer include PbTiO3, and PZT-based compounds such as lead zirconate titanate (PZT; Pb(Zr1xe2x88x92y, Tiy)O3, where O less than y less than 1) which is a solid solution of PbZrO3 and PbTiO3 having a perovskite structure, PLZT which is a metal oxide obtained by adding La to PZT, and PNZT which is a metal oxide obtained by adding Nb to PZT.
The crystallization temperature of the above-described materials for the ferroelectric layer may be varied by shifting their compositions away from the stoichiometric compositions.
The ferroelectric material layer may be obtained by first forming a ferroelectric film and then patterning the ferroelectric film in a later process. In some cases, the patterning may be omitted. The ferroelectric thin-film may be formed by a method suitable for the material used in the ferroelectric thin-film, such as the MOCVD process, pulse laser ablation process, sputter method and sol-gel method. The ferroelectric film may be patterned by an anisotropic reactive ion etching (RIE) method.
In the present invention, configurations in which the first electrode is formed under the ferroelectric layer and the second electrode is formed above the ferroelectric layer (that is, the first electrode corresponds to a lower electrode and the second electrode to an upper electrode), or in which the first electrode is formed above the ferroelectric layer and the second electrode is formed under the ferroelectric layer (that is, the first electrode corresponds to the upper electrode and the second electrode to the lower electrode) may be adopted. It is preferable from the standpoint of wiring structure simplification that the plate line extend from the second electrode. A structure in which the first electrode is shared includes a configuration in which the first electrode of a stripe form is formed, and the ferroelectric layer is formed so as to cover the entire surface of the first electrode. In such a structure, the areas where the first electrode, the ferroelectric layer and the second electrode overlap correspond to memory cells. Other examples of the structure in which the first electrode is shared includes a structure where ferroelectric layers are individually formed in predetermined areas of the first electrode and the second electrodes are formed on the ferroelectric layers, or a structure where the first electrodes are individually formed in predetermined surface areas of a wiring layer, the ferroelectric layers are formed on each of the first electrodes and the second electrodes are formed on the ferroelectric layers, but the structure is, by no means, limited thereto.
Further, in the present invention, for the case where the first electrode is formed under the ferroelectric layer and the second electrode is formed above the ferroelectric layer, it is preferable that the first electrode of the memory cell have a so-called damascene structure; and for the case where the first electrode is formed above the ferroelectric layer and the second electrode is formed under the ferroelectric layer, it is preferable that the second electrode of the memory cell have a so-called damascene structure; both of which are preferable in the present invention from the standpoint of forming the ferroelectric layer on a planar foundation.
In the present invention, as the material for the first or second electrode, Ir, IrO2xe2x88x92X, IrO2xe2x88x92X/Ir, SrIrO3, Ru, RuO2xe2x88x92X, SrRuO3, Pt, Pt/IrO2xe2x88x92X, Pt/RUO2xe2x88x92X, Pd, a layered structure of Pt/Ti, a layered structure of Pt/Ta, a layered structure of Pt/Ti/Ta, La0.5Sr0.5CoO3 (LSCO), a layered structure of Pt/LSCO and YBa2Cu3O7, where 0xe2x89xa6X less than 2, may be cited. It should be noted that in the above expressions of the layered structures, materials placed before the xe2x80x9c/xe2x80x9d contact the ferroelectric layer. The first and second electrodes may be formed with the same material, with the same kind of materials, or with different kinds of materials. The first and second electrodes may be formed by first forming a conductive layer of the first or second electrode, and then patterning the conductive layer in a later process. The conductive layer may be formed by a method suitable for the material used in the conductive layer, which includes a sputter method, reactive sputter method, electron beam deposition method, MOCVD method and pulse laser ablation process. The conductive layer may be patterned, for example, by the ion milling method or RIE method.
The selection transistor may be configured with a MIS-FET or MOS-FET. Materials which may be used for the data line include impurity-doped polysilicon or refractory metal materials. The selection transistor and the first electrode, the selection transistor and the data line may be connected via a connection hole, and the connection hole may be obtained by embedding a tungsten plug or polysilicon doped with impurities.
In the present invention, examples of materials which may be used for the insulation layer include silicon oxide (SiO2), silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG and LTO.
In the present invention, binary data which constitute digital data are written (stored) in each of the plurality of memory cells. When these data are read out simultaneously, the electric potential appearing across the data line varies depending on the data stored in the individual memory cells. Thus, digital data may be converted to analog data with a simple configuration. Further, as the data herein are stored in the ferroelectric layer, the memory is non-volatile.
In the present invention, a configuration in which a plurality of the D/A converters are juxtaposed in an array (hereinafter, such a configuration will be referred to as a D/A converter array for convenience), and the plate line of the memory cells in the individual ferroelectric non-volatile semiconductor memories is shared. As a result, high-speed conversion of a large volume of digital data to analog data becomes possible. In addition, by providing, for example, 2 such D/A converter arrays, digital data may be inputted into one of the D/A converter arrays while analog data is outputted from the other D/A converter array, thereby making it possible to convert a still larger volume of digital data to analog data at an even higher speed.
An operational principle of the memory cell will be explained below. The memory cell referred to herein is one in which changes in the amount of charge accumulated in the ferroelectric layer is detected through the use of high-speed polarization inversion and residual polarization of the ferroelectric thin-film, and in which high-speed rewriting is possible. Reading and writing data from and in the memory cell is performed through an application of the Pxe2x88x92E(V) hysteresis loop of a ferroelectric material as shown in FIG. 17. That is, the ferroelectric layer will show residual polarization when an external electric field is applied thereto and is then removed. The residual polarization of the ferroelectric layer will be +Pr when the external electric field is applied in the positive direction, and will be xe2x88x92Pr when the external electric field is applied in the negative direction. Here, the state in which the residual polarization is +Pr (see point D in FIG. 17) is taken to be xe2x80x9c0,xe2x80x9d and the state in which the residual polarization is xe2x88x92Pr (see point A in FIG. 17) is taken to be xe2x80x9c1.xe2x80x9d
In order to determine whether the status is xe2x80x9c1xe2x80x9d or xe2x80x9c0,xe2x80x9d an electric field in the positive direction, for example, is applied to the ferroelectric layer. As a result, the polarization status of the ferroelectric material layer becomes that indicated by point xe2x80x9cCxe2x80x9d in FIG. 17. If the data was xe2x80x9c0,xe2x80x9d the polarization status of the ferroelectric layer changes from xe2x80x9cDxe2x80x9d to xe2x80x9cC.xe2x80x9d On the other hand, if the data was xe2x80x9c1,xe2x80x9d the polarization status of the ferroelectric layer changes from xe2x80x9cAxe2x80x9d to xe2x80x9cCxe2x80x9d via xe2x80x9cB.xe2x80x9d That is, polarization inversion of the ferroelectric layer does not occur when the data is xe2x80x9c0,xe2x80x9d but does occur when the data is xe2x80x9c1.xe2x80x9d As a result, there is generated a difference in the amount of charge accumulated in the memory cells (capacitor portion), and the accumulated charge is detected as a signal current.
According to the present invention, in writing binary data constituting digital data in each of a plurality of memory cells and simultaneously reading out the data, the electric potential appearing across the data line varies depending on the data stored in the individual memory cells. Thus, digital data may be converted to analog data with a simple construction. Moreover, since the data is stored in the ferroelectric layer, it is non-volatile, which allows for temporal controlling of the output of the converted analog data based on external or internal signals. No separate device nor storage medium for holding or editing the analog data is necessary, and it also makes it possible to output low-frequency analog data depending on capabilities of a device to which the analog data is outputted, or to output the stored data as analog data as required based on an external trigger. The present invention also enables high-speed conversion of a large volume of digital data to analog data.